The present invention relates to integrated circuit (IC) chip reliability and, more particularly, to a method for improving IC chip reliability using reliability-optimized failure mechanism targeting when selecting and implementing changes to processes in the manufacturing line.
More particularly, various failure mechanisms can cause the components (e.g., devices, interconnects, etc.) of an integrated circuit (IC) chip to degrade. These failure mechanisms include, but are not limited to, time-dependent dielectric breakdown (TDDB) of the gate dielectric layer or between metal lines, hot carrier injection (HCI), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), soft error rate (SER), retention disturbance, stress migration (SM) (also referred to as stress-induced voiding (SIV)) and electromigration (EM). Over time these failure mechanisms can impact performance (e.g., operating speed) and/or lead to IC chip failure.
Reliability of an IC chip (also referred to herein as the expected useful life of the IC chip) can be defined in terms of the expected minimum amount of time or, more particularly, the expected minimum number of power-on hours (POHs) during which an IC chip can be expected, with a specified probability, to perform without fail. Reliability is typically determined as a function of various failure mechanisms. Specifically, designers have realized that process parameter variations have a significant impact on IC chip performance (e.g., on operating speed, as indicated by delay). Such process parameter variations are due to variations that occur during manufacturing and include, but are not limited to, variations in channel length, channel width, doping, spacer width, etc. To determine reliability, reliability simulators model the various failure mechanisms in order to set the fail rates associated with those failure mechanisms across the full process distribution for the design. The full process distribution for the design refers to the performance range of IC chips manufactured according to the design, given a nominal operating voltage. This performance range extends from relatively fast IC chips (e.g., 3σ fast IC chips) at one end of the process distribution (i.e., the “fast” end of the process distribution) to relatively slow IC chips (e.g., 3σ slow IC chips) at the opposite end of the process distribution (i.e., the “slow” end of the process distribution). When improvements are subsequently made to the manufacturing line (i.e., to processes performed within the manufacturing line) with the goal of improving IC chip reliability, it is typically assumed that the impact of those improvements will be uniform across the full process distribution.